This invention relates to a semiconductor device including bipolar transistors, and more particularly to a semiconductor device for integrated injection logic capable of reducing the power consumption and the signal propagation delay time.
In the case of forming bipolar transistors into an IC, it is necessary to completely isolate them from each other. This, however, makes the resulting IC construction complicated, which renders also complicated the manufacturing process of IC, and in addition causes an increase in power consumption. Conventionally, therefore, difficulties are encountered in constructing bipolar transistors into an LSI (Large Scale Integrated circuit) as compared with the formation of MOS transistors into an LSI. Recently, however, a fundamental structure of I.sup.2 L (Integrated Injection Logic) or MTL (merged Transistor Logic) has been exploited to render easier the formation of bipolar transistors into an LSI. According to this fundamental structure, through integrating ordinary planar bipolar transistors as upside-down operated transistors whose collector and emitter are constituted by the emitter and collector of those bipolar transistors, the isolation of the bipolar transistors from each other becomes unnecessary to cause not only an increase in the integrating density but also a decrease in the power consumption. The outline of the abovementioned fundamental structure will now be described by reference to FIGS. 1 and 2. Referring to FIG. 1, on an n.sup.+ substrate 1 connected to a ground terminal G an n layer 2 is formed, for example, by epitaxial growth method. In this n layer 2 a p layer 3 is formed by diffusion. Further, in this p layer 3, for example, two n.sup.+ layers 4a, 4b are formed by diffusion in a manner spaced from each other. Further, a p.sup.+ layer 5 is formed by diffusion in the n layer 2 in a manner adjacent the p layer 3. The p layer 3, n.sup.+ layers 4a, 4b, and p.sup.+ layer 5 are connected to an input terminal IN, output terminals OUT.sub.1, OUT.sub.2 and charge injection terminal +E, respectively. A semiconductor device shown in FIG. 1 can be represented by an equivalent circuit shown in FIG. 2, that is, a combined circuit of an npn transistor Q.sub.1 and a pnp transistor Q.sub.2. The npn transistor Q.sub.1 is a multi-collector type upside-down operated transistor wherein the collector is constituted by the n.sup. + layers 4a, 4b; the base by the p layer 3; and the emitter by the n layer 2. The pnp transistor whose emitter, base and collector use the p.sup.+ layer 5, n layer 2 and p layer 3, respectively. The pnp transistor Q.sub.2 is intended to inject carriers into the base of the npn transistor Q.sub.1 and is called"injector". The circuit of FIG. 2 is thus constructed such that the inverted signals OUT.sub.1, OUT.sub.2 of an input signal IN are obtained with a D.C. voltage of +E applied to the emitter of the transistor Q.sub.2. The fundamental structure shown in FIG. 1, the equivalent circuit shown in FIG. 2 and the operation of the inverter are described in Wiedmann, S, "Injection-Coupled Memory". IEEEJ. Solid State Circuits, Vol, SC-8, No. 5, Oct. 1973, p332 to 337.
FIG. 5 shows the relationship between the mean power consumption and mean propagation delay time of the above-mentioned I.sup.2 L. When consideration is given to a product of power consumption and delay time, the product with respect to the I.sup.2 L is relatively small as compared with that with respect to a TTL (Transistor-Transistor-Logic), and coincides with a 1 P. J. (1 Pico Joule) line as indicated by a solid line in FIG. 5. But the delay time is saturated at a point of about 10 nanosecond. As a result, even when the power consumption was increased, the delay time could not be shortened any further.
Accordingly, it is the object of the invention to provide a semiconductor device for integrated injection logic capable of reducing the signal propagation delay time and the power consumption.
A semiconductor device of the invention comprises a semiconductor substrate of a first conductivity type, a signal input region of a second conductivity type provided in the substrate, at least one signal output region of the first conductivity type formed in the signal input region, a charge injection region provided closely to the signal input region and forming a pn junction with the substrate and having a high impurity concentration, and electrodes provided for the substrate, signal input region, signal output region, and charge injection region, respectively, whereby to obtain an inverted output of an input signal by applying a forward bias voltage to the pn junction, said signal input region including a first region of the second conductivity type having a lower impurity concentration than the charge injection region, and a second region provided in at least part of the surface of the first region and having the same conductivity type as that of the first region and having a higher impurity concentration than the first region, said second region being adjoined to the signal output region and connected to the signal input electrode.
According to the invention, the signal propagation delay time can be remarkably decreased by causing a large reduction in lateral resistance of the signal input region. Simultaneously, the linear decreasing characteristic of the propagation delay time relative to the power consumption is improved to provide a semiconductor device wherein the delay time is not saturated up to sub-nanosecond.